HET Seminar | Patrick Hayden, Stanford University | "Fault-tolerant qubit from a constant number of components" | via Zoom

Mon, Feb 15, 2021, 2:30 pm
via Zoom

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Abstract: With gate error rates in multiple technologies now below the threshold required for fault-tolerant quantum computation, the major remaining obstacle to useful quantum computation is scaling, a challenge greatly amplified by the huge overhead imposed by quantum error correction itself. I’ll discuss a new a fault-tolerant quantum computing scheme that can nonetheless be assembled from a small number of experimental components, potentially dramatically reducing the engineering challenges associated with building a large-scale fault-tolerant quantum computer. The architecture couples a single controllable qubit to a pair of delay lines which terminate in a detector. Below a threshold noise value for the controllable qubit, the logical error rate decays exponentially with the square root of the delay line coherence time. The required gates can be implemented using existing technologies in quantum photonic and phononic systems. With continued incremental improvements in only a few components, we expect these systems to be promising candidates for demonstrating fault-tolerant quantum computation with comparatively modest experimental effort.

Based on joint work with Kianna Wan, Soonwon Choi, Isaac Kim and Noah Shutty.